Field
This disclosure relates to a capacitorless DRAM, and more particularly to a capacitorless DRAM capable of implementing multi-bit and a manufacturing method thereof.
Description of the Related Art
A dynamic random access memory (DRAM), i.e., one of semiconductor parts which are necessarily used in computing, consists of one transistor and one capacitor. However, in a conventional DRAM, the size of the capacitor should become smaller with the reduction of the size of the device. Therefore, it has been believed that it is difficult to obtain a capacitor having a sufficiently high capacitance. Also, when an embedded chip is formed together with other devices, a process of forming the capacitor acts as an obstacle due to a high level difference of the capacitor. Therefore, attention is paid to a capacitorless DRAM capable of storing data without the capacitor which causes complex processes. Since the capacitorless DRAM does not use the capacitor, it has big advantages in terms of a degree of integration and the manufacturing cost thereof, compared with the conventional DRAM.
FIG. 1a is a cross sectional view showing schematically an operation principle of a conventional capacitorless DRAM. FIG. 1b is an energy band diagram of the conventional capacitorless DRAM. The capacitorless DRAM is manufactured by using a floating body device and a Silicon-On-Insulator (SOI) substrate or a common silicon bulk substrate. A predetermined voltage is applied to a gate 2 and a drain 4 of the transistor, so that excess holes are generated in the channel of the drain 4 by impact ionization 9. Since there is no outlet which allows the generated excess holes to escape, they are accumulated within a body 5. As compared with the transistor where the body 5 does not have the hole, the transistor having the accumulated holes has differences in a threshold voltage and a current level. Here, a state ‘0’ and a state ‘1’ are distinguished by using the differences.
A state where the holes have been accumulated within the body 5 is referred to as the state ‘1’. A state where all the holes have escaped from within the body 5 is referred to as the state ‘0’. That is, data of the conventional capacitorless DRAM could exist only in two states, i.e., the state ‘0’ and the state ‘1’. This means that only one bit of information can be stored. In other words, since the conventional capacitorless DRAM has a structural limit that has only one body region (channel region), it cannot operate at greater than 2 bits.